Currently, the Signal Integrity (SI) and the Reliability Verification (RV) groups are looking for a student who is interested in timing analysis and its dependence on IRDrop (static and dynamic). Both groups would like to combine their expertise to prepare timing analysis for future requirements regarding the influence of IRDrop. The task will include the setup of VoltageStorm in combination with CeltIC and with Primetime, a comparison of both flows and the evaluation of the impact of the IRDrop on the timing. The comparison and the evaluation will also include simulations with Spice and other internal tools.
Qualifications
You should possess a Bachelor or a Master of Science degree in Electronic Engineering or Computer Engineering. You should already have started your studies and successfully participated courses in basic electronic and semiconductor engineering. Additional qualifications include:
- Knowledge in electronic design automation, and Application Specific Integrated Circuit (ASIC) or Ion Chromatography (IC) design and/or verification
- Some knowledge in Verilog*, Visual* C++, UNIX*, HTML, (PHP) and measurement equipment
- Basic understanding of the silicon development cycle
- Communication skills
- Proficiency in written and spoken English
Job Category Engineering
Location GermanyGermany, Braunschweig
Full/Part Time Full Time
Job Type Student/Intern
Regular/Temporary Regular
Additional Information
Posting Date Oct 12, 2007, 12:21 PM, (UTC +5:30)
Apply Before Oct 12, 2008, 05:29 AM, (UTC +5:30)
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